State Assignment for Initializability of Synchronous Finite State Machines

It is well known that state encoding can in uence the logic initializability of an FSM implementation. If the sole objective of an \optimal" state assignment is to minimize the amount of logic, one may end up with implementations that are logically uninitializable. That is, a 3-valued (0,1,X) logic simulator may not be able to initialize the circuit even when its FSM has a synchronizing sequence. Initializability is required for (most) non-scan ATPG's such as CONTEST [1] and STG [2] to work e ectively. Traditionally, several di erent approaches to initializability have been used. Each of these assumes di erent models of initializability (such as singleor multi-vector) and of simulation (such as true-value or 3-value). Further, while the Wehbeh and Saab [3] algorithm analyzes the gate-level circuit to determine if it is initializable, there are other methods that enable one to synthesize for initializability. We follow the approach of Cheng and Agrawal [4,5] who attempt to produce a state assignment that makes the circuit initializable.